8Gb: x16 TwinDie Automotive DDR3L SDRAM
Description
TwinDie 1.35V Automotive DDR3L
SDRAM
MT41K512M16 – 64 Meg x 16 x 8 Banks
Description
Options
• Configuration
– 512 Meg x 16
• TFBGA package (Pb-free) – x16
– 96-ball (8mm x 14mm) - SAC302
– 96-ball (8mm x 14mm) - SAC Q
• Timing – cycle time
– 1.07ns @ CL = 13 (DDR3-1866)
• Product certification
– Automotive
• Operating temperature
– Industrial (–40°C ≤ T C ≤ +95°C)
– Automotive (–40°C ≤ T C ≤ +105°C)
• Revision
The 8Gb (TwinDie) DDR3L SDRAM (1.35V) uses two
Micron 4Gb DDR3L SDRAM x8 die for a 2 byte x16 device in one package. Refer to Micron’s 4Gb DDR3L
SDRAM data sheet (x8 option) for specifications not
included in this document, specifications for base part
number MT41K512M8 correlate to TwinDie manufacturing base part number MT41K512M16.
Features
• Uses two x8, 4Gb Micron die to make one x16 package
– Single rank TwinDie
– One external ZQ ball and one internal ZQ connected to V SSQ through an embedded serial resistor
• VDD = V DDQ = 1.35V (1.283–1.45V)
• Backward compatible to V DD = V DDQ = 1.5V ±0.075V
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of –40°C to +105°C
– 64ms, 8192-cycle refresh at –40°C to +85°C
– 32ms at +85°C to +105°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
• AEC-Q100
• PPAP submission
• 8D response time
CCM005-1005363231-10357
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Note:
1
Marking
512M16
VRN
VRP
-107
A
IT
AT
:P
1. Not all options listed can be combined to
define an offered product. Use the part catalog search on http://www.micron.com for
available offerings.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2018 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
8Gb: x16 TwinDie Automotive DDR3L SDRAM
Description
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
-107
1866
13-13-13
tRCD
tRP
(ns)
13.91
(ns)
13.91
CL (ns)
13.91
Table 2: Addressing
Parameter
512 Meg x 16
Configuration
64 Meg x 8 x 8 banks x 2 die
Die per package
2
Refresh count
8K
Row address
64K (A[15:0])
Bank address
8 (BA[2:0])
Column address
1K (A[9:0])
Page size per die
1KB
Figure 1: DDR3L Part Numbers
Example Part Number: MT41K512M16VRP-107 AAT:P
Configuration
Package
Speed
Revision
{
MT41K
:
Configuration
512 Meg x 16
:P
Mark
512M16
Package
Mark
96-ball FBGA, 8mm x 14mm
VRN
96-ball FBGA, 8mm x 14mm
VRP
Speed Grade
t CK = 1.07ns, CL = 13
Note:
Revision
Temperature
Mark
Industrial temperature
IT
Automotive temperature
AT
Mark
Certification
107
Automotive
Mark
A
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
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© 2018 Micron Technology, Inc. All rights reserved.
8Gb: x16 TwinDie Automotive DDR3L SDRAM
Description
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
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© 2018 Micron Technology, Inc. All rights reserved.
8Gb: x16 TwinDie Automotive DDR3L SDRAM
Important Notes and Warnings
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
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8Gb: x16 TwinDie Automotive DDR3L SDRAM
Functional Description
Functional Description
The TwinDie DDR3L SDRAM is a high-speed, CMOS dynamic random access memory
device internally configured as two 8-bank DDR3L SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like die tested within a monolithic die package.
The DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3L SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3L SDRAM and edge-aligned to
the data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3L SDRAM are burst-oriented. Accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and row to be accessed. The
address bits (including CSn#, BAn, and An) registered coincident with the READ or
WRITE command are used to select the rank, bank, and starting column location for the
burst access.
This data sheet provides a general description, package dimensions, and the package
ballout. Refer to the Micron monolithic DDR3L data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die
operation.
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8Gb: x16 TwinDie Automotive DDR3L SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 2: 96-Ball FBGA – x16 (Top View)
A
B
1
2
3
VDDQ
DQ13
VSSQ
7
8
9
DQ15
DQ12
VDDQ
VSS
VDD
VSS
UDQS#
DQ14
VSSQ
VDDQ
DQ11
DQ9
UDQS
DQ10
VDDQ
VSSQ
VDDQ
UDM
DQ8
VSSQ
VDD
VSS
VSSQ
DQ0
LDM
VSSQ
VDDQ
VDDQ
DQ2
LDQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
LDQS#
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
A15
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
A14
A8
VSS
C
4
5
6
D
E
F
G
H
J
K
L
M
N
P
R
T
Notes:
1. Ball descriptions listed in Table 3 are listed as “x4, x8” if unique; otherwise, x4 and x8
are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3).
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8Gb: x16 TwinDie Automotive DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 96-Ball FBGA – x16 Ball Descriptions
Symbol
Type
Description
A[15:13], A12/BC#,
A11, A10/AP, A[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See the Truth Table – Command section.
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
LDM
Input
Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is
designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,
and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for
the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
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8Gb: x16 TwinDie Automotive DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol
Type
Description
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and
DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.
UDM
Input
Input data mask: UDM is an upper-byte, input mask signal for write data. Upperbyte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ.
DQ[7:0]
I/O
Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
DQ[15:8]
I/O
Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS#
I/O
Lower byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
UDQS, UDQS#
I/O
Upper byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. DQS is center-aligned to write data.
VDD
Supply
Power supply: 1.35V (1.283–1.45V) / 1.5V ±0.075V (backward compatible).
VDDQ
Supply
DQ power supply: 1.35V (1.283–1.45V) / 1.5V ±0.075V (backward compatible). Isolated on the device for improved noise immunity.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
ZQ
Reference
NC
–
External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to VSSQ.
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
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8Gb: x16 TwinDie Automotive DDR3L SDRAM
Package Dimensions
Package Dimensions
Figure 3: 96-Ball FBGA – x16
Seating plane
0.1
A
96X Ø0.525±0.05
Dimensions apply
to solder balls postreflow on Ø0.47 SMD
ball pads.
A
Ball A1 ID
(covered by SR)
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
14 ±0.1
12 CTR
0.8 TYP
1.1 ±0.1
0.8 TYP
6.4 CTR
0.38 ±0.05
8 ±0.1
Notes:
1. All dimensions are in millimeters.
2. VRN material composition: Pb-free SAC302 (96.8% Sn, 3% Ag, 0.2% Cu) .
3. VRP material composition: Pb-free SAC Q (92.45% Sn, 4% Ag, 0.5% Cu, 3% Bi, 0.05%
Ni) .
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8Gb: x16 TwinDie Automotive DDR3L SDRAM
Functional Block Diagram
Functional Block Diagram
Figure 4: Functional Block Diagram (512Meg x 16 )
Die2
Byte 0
(64 Meg x 8 x 8 banks)
Die1
Byte 1
(64 Meg x 8 x 8 banks)
RZQ
VSSQ
ZQ
LDM
CS#
RAS#
CAS#
DQ[7:0]
LDQS
LDQS#
CK
A[15:0],
BA[2:0]
WE#
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CK#
CKE
ODT
10
UDM
DQ[15:8]
UDQS
UDQS#
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8Gb: x16 TwinDie Automotive DDR3L SDRAM
Thermal Characteristics
Thermal Characteristics
Table 4: Thermal Characteristics
Notes 1–3 apply to entire table
Parameter
Symbol
Value
Units
Notes
Operating case temperature – Industrial
TC
–40 to +95
°C
1, 2, 3, 4
Operating case temperature – Automotive
TC
–40 to +105
°C
1, 2, 3 , 4
1. MAX operating case temperature TC is measured in the center of the package, as shown
below.
2. A thermal solution must be designed to ensure that the device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs
interval refresh rate. The use of SRT or ASR must be enabled.
Notes:
Figure 5: Thermal Measurement Point
(L/2)
Tc test point
L
(W/2)
W
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8Gb: x16 TwinDie Automotive DDR3L SDRAM
Thermal Characteristics
Table 5: Thermal Impedance
ΘJA (°C/W)
Die
Rev.
P
ΘJB
(°C/W)
ΘJC
(°C/W)
Package
Substrate
Airflow =
0m/s
Airflow =
1m/s
Airflow =
2m/s
96-ball (VRN
and VRP)
Low conductivity
52.2
41.1
36.7
N/A
4.9
High conductivity
33.9
28.7
26.9
19.0
N/A
Note:
1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
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8Gb: x16 TwinDie Automotive DDR3L SDRAM
Electrical Specifications
Electrical Specifications
Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 6: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
1
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VDDQ
VDD supply voltage relative to VSSQ
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
0
95
°C
2, 3
Operating case temperature – Industrial
–40
95
°C
2, 3
Operating case temperature – Automotive
–40
105
°C
2, 3
Storage temperature
–55
150
°C
TC
TSTG
Operating case temperature – Commercial
Notes:
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are 85°C: IDD4R, IDD4W, IDD5B, and IDD7 must be derated by 5%; IDD0, IDD1,
IDD2P1, IDD3N, and IDD3P must be derated by 15%; IDD2P0, IDD2Q, IDD2N, and IDD2NT must be
derated by 40%.
2c. When TC > 95°C: all IDD values must be derated (increased) by 30% from the 85°C
specifications.
2d. When TC > 105°C: all IDDx values must be derated (increased) by 50% from the 85°C
specifications.
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8Gb: x16 TwinDie Automotive DDR3L SDRAM
Revision History
Revision History
Rev. D – 01/20
• 12/04/2019 Added package code VRP in Options, DDR3L Part Numbers figure, and
Thermal Impedance table
• 12/12/2019 Added note 3 VRP material composition: Pb-free SAC Q (92.45% Sn, 4%
Ag, 0.5% Cu, 3% Bi, 0.05% Ni) in Package Dimensions
• 12/12/2019 Removed ultra-high (–40 to +125°C) from Thermal Characteristics table
Rev. C – 04/19
• 04/10/2019 Updated DDR3L Input/Output Capacitance table: CCK, CI, and CDI_CTRL
Rev. B – 02/19
• 01/08/2019 Updated legal status to Production
• 01/08/2019 Updated DDR3L Input/Output Capacitance table in Input/Output Capacitance section
Rev. A – 08/18
• 07/26/2018 Updated thermal characteristics section
• 07/01/2018 Changed Die 0 to Die 1 in Functional Block Diagram
• 04/01/2018 Initial release for DDR3L_8Gb_x16_1_35V_Single_rank_TwinDie
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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
CCM005-1005363231-10357
DDR3L_8Gb_x16_1CS_TwinDie_V00H_Automotive.pdf - Rev. D 01/20 EN
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